1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to an intelligent power integrated circuit having a power device and a control device formed on the same substrate, and to a method for manufacturing the same.
2. Description of the Related Art
An intelligent power integrated circuit having a vertical double diffusion MOS (VDMOS) as an output device, in which a power device and a control device controlling the same are formed on the same substrate, is used for an application for controlling solenoid. The power integrated circuit usually employs the SOI structure to electrically insulate the power device from the control device. However, a buried oxide layer should be partially formed such that drain current of the VDMOS can vertically flow, so that it is difficult to manufacture the SOI structure.
Much research for realizing an intelligent power integrated circuit is currently being conducted. Here, silicon direct bonding technology by which the intelligent power integrated circuit having partially bonded SOI substrates can be obtained will be described (from "Partially Bonded SOI Substrates for Intelligent Power Ies", Solid State Device and Materials, 1995, pp. 848-850, Hiroaki Kikuchi and Kenichi Arai).
FIGS. 1A through 1E are sectional views for illustrating a method for manufacturing a conventional intelligent power integrated circuit forming a power device and a control device on the same substrate.
A buried oxide layer 12 is formed in a control device portion of a first wafer 10 of N.sup.- -type in a trench, as illustrated in FIG. 1A, formed by etching which is etched with an HF solution until a recess portion 14 of approximately 0.1 .mu.m is formed (FIG. 1B).
Subsequently, the first wafer 10 having the recess portion 14 and a second wafer 16 of N.sup.+ -type are processed in a SCI solution to remove impurity particles from a bonding surface. During the above process, native oxides layer formed on the two wafers strengthen the bonding strength, so that the bond does not separate. Then, the first wafer 10 having the recess portion 14 and the second wafer 16 are bonded at a room temperature. Subsequently, an annealing process is performed to strengthen the bonding strength of the bonded wafers. As a result, a gap G is formed between the buried oxide layer 12 and the second wafer 16 of N.sup.+ -type(FIG. 1C).
Then, the first wafer 10 of N.sup.- -type is polished to form an active layer. At this time, the thickness of the active layer, which is the thickness of the polished first wafer, is chosen to achieve a desired breakdown voltage between a source of a VDMOS and a drain thereof to be formed (FIG. 1D). Subsequently, a control device is formed in an active layer (a control device portion) on the buried oxide layer 12 and the gap G, and the VDMOS of a power device is formed in other regions, i.e., a power device portion (FIG. 1E).
The method for manufacturing an intelligent power integrated circuit IC using the above-described direct bonding technology is for manufacturing the SOI substrate partially formed on the second wafer 16 of N.sup.+ -type of a high concentration. At this time, the control device is formed on the SOI structure, and a power device of VDMOS is formed in a region other than the SOI structure. That is, the buried oxide layer is partially formed on the first wafer, which is bonded to the second wafer using the silicon direct technology, to thereby easily manufacture the intelligent power integrated circuit in which the VDMOS of the power device and the control device are formed on the same wafer, i.e., on the second wafer 16 of N.sup.+ -type.